Conventional computer memory subsystems are often implemented using memory modules. A computer circuit board is assembled with a processor having an integrated memory controller, or coupled to a separate memory controller, connected by a memory bus to one or more memory module electrical connectors (the bus may also connect to additional memory permanently mounted on the circuit board). System memory is configured according to the number of and storage capacity of the memory modules inserted in the electrical connectors.
As processor speeds have increased, memory bus speeds have been pressured to the point that the multi-point (often referred to as “multi-drop”) memory bus model no longer remains viable. Referring to FIG. 1, one current solution uses a “point-to-point” memory bus model employing buffered memory modules. In FIG. 1, a computer system 100 comprises a host processor 105 communicating across a front-side bus 108 with a memory controller 110 that couples the host processor to various peripherals (not shown except for system memory). Memory controller 110 communicates with a first buffered memory module 120 across a high-speed point-to-point bus 112. A second buffered memory module 130, when included in system 100, shares a second high-speed point-to-point bus 122 with first memory module 120. Additional high-speed point-to-point buses and buffered memory modules, such as buses 132 and 142 and memory modules 140 and 150, can be chained behind memory module 130 to further increase the system memory capacity.
Buffered memory module 140 is typical of the memory modules. A memory module buffer (MMB) 146 connects module 140 to a host-side memory channel 132 and a downstream memory channel 142. A plurality of memory devices (Dynamic Random Access Memory Devices, or “DRAMs” like DRAM 144, are shown) connect to memory module buffer 146 through a memory device bus (not shown in FIG. 1) to provide addressable read/write memory for system 100.
FIGS. 2a and 2b show, respectively in top and side view, one possible physical appearance for a Dual In-line Memory Module (DIMM) embodiment of memory module 140. A set of card edge connectors 148 provide electrical connection for host-side and downstream memory channels, reference and power supply voltages, clock signals, etc. MMB 146 is centrally located on one side of module 140, flanked on each side by four DRAM devices 144. Ten more DRAM devices occupy the opposite side of module 140. MMB 146 conducts all memory transactions with the DRAMs.
As an exemplary memory transfer, consider a case in which processor 105 needs to access a memory address corresponding to physical memory located on memory module 140. A memory request is issued to memory controller 110, which then sends a command, addressed to memory module 140, out on host memory channel 112. The MMB of buffered memory module 120 receives the command, retimes it, if necessary, and resends it on memory channel 122 to the MMB of buffered memory module 130. The MMB of buffered memory module 130 next receives the command, retimes it, if necessary, and resends it on memory channel 132 to MMB 146 on memory module 140. MMB 146 detects that the command is directed to it, decodes it, and transmits a DRAM command and signaling to the DRAMs controlled by that buffer.
When the command issued by memory module 140 is a write command, the command includes a write address and is accompanied by the data to be written to that address. The data is of the same “width” as the memory, where width represents the number of bits of data that are stored when a write to a single address is initiated. When the command issued by memory module 140 is a read command, the command includes a read address, and the memory module is expected to return data read from the read address a few clock cycles later.
Some DRAMs and module buffers support “burst write” and “burst read” operations. When a burst-operation-capable DRAM receives a burst operation, the write or read address is defined to be the starting address for a multi-cycle operation. For instance, in a four-memory-width burst write, write data is supplied to the module DRAMs during four successive clock cycles, and each DRAM is expected to store the write data in four successive addresses beginning with the write address. In a four-memory-width burst read, each DRAM reads data from four successive addresses and transmits the data during four successive clock cycles. In both cases, buffer 146 must comprehend the burst length in order to appropriately direct burst data between its DRAMs and host-side memory channel 132.